Except where otherwise indicated herein, the electrooptic components employed in typical embodiments of the present invention are now well known. Convenient ways of making them are described in the above mentioned patents and applications and in the references cited therein and herein.
The terms "reflect", "reflective", etc. are used herein broadly to relate to any changing of direction or bending of the general type commonly provided by mirrors, gratings, beam splitters, and the like. In the Bragg gratings and beam splitters employed in typical embodiments of the present invention, the reflections are of course provided by the phenomenon more particularly called diffraction. So the words "reflection" and "diffraction", and their corresponding verbs, adjectives, etc., can be considered to be substantially synonyms as used herein, especially in describing and defining typical features of the invention.
The term "IOC" is used herein as an acronym for "integrated optical circuit". "SAW" is an acronym for "surface acoustical wave". "IOSLM" is an acronym for "integrated optical spatial light modulator". "VLSI" means "very large scale integration". "PISO" means "parallel in, serial out". "SIPO" means "serial in, parallel out". "D/A" means "digital to analog (converter)".
The disclosure in the December 1982 copending application for Systolic Array Processing includes the paper by H.J. Caulfield, et al.sup.(8) wherein it is shown how certain algorithms for matrix-vector multiplication can be implemented using acoustooptic cells for mulitplication and input data transfer and using CCD (change coupled device) detector arrays for accumulation and output of the results. No 2-D matrix mask is required; matrix changes are implemented electronically. A system for multiplying a 50-component nonnegative-real matrix is described. Modifications for bipolar-real and complex-valued processing are possible, as are extensions to matrix-matrix multiplication and multiplication of a vector by multiple matrices.
During the last several years, Kung and Leiserson at Carnegie-Mellon University.sup.(1,9) have developed a new type of computational architecture which they call "systolic array processing". Although there are numerous architectures for systolic array processing, a general feature is a flow of data through similar or identical arithmetic or logic units where fixed operations, such as multiplications and additions, are performed. The data tend to flow in a pulsating manner, hence the name "systolic". Systolic array processors appear to offer certain design and speed advantages for VLSI implementation over previous calculational algorithms for such operations as matrixvector multiplication, matrix-matrix multiplication, pattern recognition in context, and digital filtering.
The December 1982 application deals with improving systolic array processors by using optical input and output as well as new architectures for optical signal processing, particularly for multiplications involving at least one matrix; and it points out that many other operations can be performed in an analogous manner.
The following disclosure includes, with slight revision, relevant portions of the paper by C.M. Verber and R.P. Kenan, "Integrated Optical Circuits for Numerical Computation"; in Integrated Optics III, Proc. SPIE, vol. 408, 1983, pp. 57-64. (Paper Number408-10 of the SPIE (Society of Photo-Optical Instrumentation Engineers)), SPIE's Technical Symposium East '83, held in Arlington, Va., April 4-8, 1983; presented there orally on April 5, 1983.) In the paper, recent developments in the design of integrated optical circuits for performing optical numerical computations are discussed. The use of systolic architectures for these IOC's is described and the natural marriage of IOC's with the systolic concept is discussed. Examples include optical binary correlation, polynomial evaluation, and matrix multiplication.
There has recently been an increasing interest in the application of optical techniques to the solution of a variety of computational problems. The reasons most commonly cited for this interest are the high processing speeds and the low power consumption which are potential characteristics of optical analog devices, especially if the problem and the algorithm are well chosen.
The approach to computer design known as systolic array architecture was developed by Kung.sup.(1) and others as a method of approaching the problem of VLSI computer design. The basic guidelines are:
a. Each datum should be fetched from memory only once to avoid the "von Neuman bottleneck".
b. Each chip should contain only a small number of different processor subunits, although these subunits may be repeated many times on each chip.
c. Connections between subunits should be only to nearest neighbors to facilitate the rapid flow of data and to simplify fabrication.
We would be hard pressed to compile a better list of design guidelines for integrated optical circuits (IOCs).
a. We do not yet have available an optically addressable memory for IOCs, although some of Nishihara's.sup.(2) surface holograms may be adaptable for this purpose. It is therefore essential that the recourse to memory be minimized since the act of fetching data from a digital store is much slower than the rate at which the IOC is capable of using that data.
b. At this stage in the development of IOC technology, we have only a small number of operational building blocks available to us. The second guideline is therefore compatible with IOC technology, if only by default.
c. The third guideline is perhaps not as important for optical as for electronic systems since it is possible to have optical carriers intersect in either planar or in channel.sup.(3) configurations without causing significant crosstalk. Complex interconnection schemes can therefore be implemented without requiring a multilayer structure. However, since the progress of the data through an optical processor is controlled by the speed of light in the device and not by a digital clock, it is necessary to pay attention to path lengths in high-speed devices to assure that proper synchronism of the data flow is maintained.
There are several obvious advantages to using integrated as opposed to bulk optical techniques for the implementation of high-speed computational algorithms. Perhaps the most important is that a variety of high-speed integrated-optical modulators.sup.(4) and switches.sup.(5) have already been developed and that these require electrical drive signals which are several orders of magnitude less than comparable bulk components. In addition, the integrated systems tend to be more compact than conventional optical systems and lend themselves to mass production by more or less conventional photolithographic techniques. A major shortcoming of the IOCs is that they are not capable of the same flexibility in handling two-dimensional computations as are the bulk devices. A hybrid approach seems to be the solution to this problem.
The devices to be described rely heavily on the use of electrooptically induced gratings. Such gratings are generated via the electrooptic effect using the fringing field from a set of interdigital surface electrodes. The basic electrode structure is illustrated in FIG. 1. The electric field immediately below the electrodes is normal to the waveguides surface, and at the surface in the gap it is tangential to the waveguide surface. Both of these fields are periodic with period equal to four line widths (if the line and gap widths are the same). The amplitudes of the index variations induced by the two fields are not, however, equal because they generally invoke different electrooptic coefficients. The net effect of the electrode configuration is to produce a complicated index profile. The fields, to which the refractive index variations are proportional, have been given by Engan.sup.(6) in a Fourier series; for our uses, only the fundamental component is important. The presence of two fields causes the index pattern to be shifted relative to the electrode structure, that is, the maximum of the index modulation does not occur at the centers of the gaps or of the electrode lines, but is displaced somewhat.
The induced gratings can be operated at high efficiency, if desired, using low voltages. A typical result is 95% efficiency at voltages of 4-10 volts for a grating with electrode lines 2 mm long and a period of 8-15 .mu.m. The diffraction efficiency of a grating having many fingers appears to follow Kogelnik's.sup.(7) theory in form, but typically does not reach 100% efficiency. The reason for this may be the incomplete overlap of the electric field with the optical field because of the exponential decay of the former with depth into the waveguide. Finally, we mention that the capacitance of the surface electrodes on y-cut LiNbO.sub.3 is about 0.5 pf/mm of finger length/finger pair, or 1 pf/finger pair for 2 mm long fingers.
Electrooptic gratings are capable of performing simple arithmetic (or logic) operations on analog (or binary) voltage signals. The simplest such operation is performed using the basic element pictured in FIG. 1. The diffracted light beam has intensity equal to .eta..times.I.sub.o, and .eta. is determined by the voltage difference between the two electrodes. For binary (two-level) signals, the result is the exclusive OR (EXOR) logic operation. For analog voltages, the result is a nonlinear function of the voltages, but for small signals, it is proportional to (V.sub.1 -V.sub.2).sup.2, the square of the voltage difference.
To multiply two signals together, we use the "herringbone" structure shown in FIG. 2. This is essentially two grating-inducing electrode systems using slanted fingers and placed so that the output of the first is the input to the second. In FIG. 2, the gratings share one electrical lead, the ground, but this is not required. The output here is the input intensity multiplied by the product of the efficiencies of the two gratings. Again, because the grating response is nonlinear in the voltages, some arrangement must be used to linearize the device.